EZ-DSPCPU-52 Single Board Computer

The EZ-DSP CPU-52 provides a low cost method for debugging andevaluating the TMS320BC52 Texas Instruments microprocessor. The'C52's advanced Harvard type architecture maximizes theprocessing power by maintaining two separate memory busstructures, program and data, for full-speed execution.Instructions support data transfers between the two spaces. Thisarchitecture permits coefficients stored in program memory to beread into the RAM, eliminating the need for a separatecoefficient ROM. It also makes available immediate instructionsand subroutines based on computed values. Control signals andinstructions provide floating-point support, block memorytransfers, communication to slower off-chip devices andmultiprocessing implementations.

The EZ-DSP Manager software is used to communicate (through ahost computer or terminal's serial port) with the EZ-DSP CPU-52Single Board Computer. The EZ-DSP Manager software allows you tomodify and display on-board user data/program memory, disassembleprogram memory (to the screen or dump to a file), assemble sourcecode and download corresponding hex files, execute user programs,set breakpoints and display "watch" variables, modifyand display CPU register contents and display the contents ofuser memory "graphically" on the screen.

The EZ-DSP Manager allows you to appreciate the features andthe ease of operation of using this "menu driven"monitor program. Unlike other "monitor" programs thatrequire you to memorize and type numerous commands, the EZ-DSPManager software has all of the commands listed for you incategorized pull down menus.

• In order to run the EZ-DSP Manager software, the following system is required:
• IBM Personal Computer (or compatible)
• MS-DOS (version 3.0 or later)
• Minimum 640K RAM memory
• EGA or VGA graphics adapter card
• RS-232 serial interface port
• A mouse is suggested but is not required
• A hard disk is suggested but is not required

• TMS320BC52 CPU in a 100 pin thin quad flat package.
• 25-, 35- and 50-ns Single-Cycle Instruction execution time with 3-V or 5-V operation.
• Single-Cycle 16 x 16-Bit Multiply/Add.
• 128K Words total Data/Program space.
• 4K x 16-Bit Single access on-chip program ROM.
• 1K x 16-Bit Dual access on-chip program/data ROM.
• Full-Duplex synchronous serial port for CODEC interface.
• Hardware or software wait state generation.
• On-chip timer for control operations.
• Repeat instructions for efficient use of program space.
• Multiply-by-two and divide-by-two clocking options.
• Block moves for data/program management.
• On-chip scan based emulation logic.
• Low power dissipation and power down modes:
• • 47mA (2.35 mA/MIP) at 5V, 40-MHz
  • 3 mA at 5V, 40-MHz (typical IDLE2)
  • 5 uA at 5V, clocks off (typical standby)

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